The present invention relates to a latch-type sensing circuit comprising a combination of two inverters, and a program-verify circuit having the above latch-type sensing circuit.
In recent years, developments have been aggressively made on a memory cell having a floating gate and a control gate and being electrically re-writable (to be simply abbreviated as "memory cell" hereinafter). The memory cell is composed of one memory element or a plurality of memory elements depending upon its type, and these memory cells can be classified, for example, into a type of a NOR type nonvolatile semiconductor memory cell (to be referred to as "NOR type memory cell" hereinafter) and a type of a NAND type nonvolatile semiconductor memory cell (to be referred to as "NAND type memory cell"). Further, with regard to a data readout method and a program-verify method (data writing method), various methods have been and are proposed depending upon types of the memory cells.
A program-verify circuit in a potential sensing-type memory cell has a potential sensing circuit for sensing a potential of a bit line. The potential sensing circuit is composed of a latch-type sensing circuit comprising a combination of two CMOS inverters as shown in FIG. 23. One CMOS inverter comprises a p-channel type MOS transistor TR.sub.1 and an n-channel type MOS transistor TR.sub.2, and the other CMOS inverter comprises a p-channel type MOS transistor TR.sub.3 and an n-channel type MOS transistor TR.sub.4. The latch-type sensing circuit has transistors for switching TR.sub.A, TR.sub.B, TR.sub.C and TR.sub.D. The latch-type sensing circuit can convert an analog potential of a bit line to a binary data by comparing a bit line output potential V.sub.BL with a reference potential V.sub.ref, and retain (latch) it therein.
Further, for materializing a large capacity and a lower cost with regard to the memory cell, the technique of multi-bit (multilevel) storage for storing data of 2 bits or more, i.e., a ternary or multi-valued data in one memory element is attracting attention. When the multi-valued data is stored in a memory cell, it is essential to sense a multilevel bit line output potential V.sub.BL discriminatingly.
In the conventional latch-type sensing circuit shown in FIG. 23, however, the threshold value of logical inversion of a CMOS inverter is pre-determined depending upon a transistor size and the like given during the designing of the circuit, and is fixed. The threshold value of logical inversion of the CMOS inverter cannot be changed by means of system of a circuit in the memory cell or during the performance of the memory cell. Therefore, for sensing a multilevel bit line output potential V.sub.BL discriminatingly, it is required to provide a plurality of latch-type sensing circuits and switch the latch-type sensing circuits depending upon multi-valued date stored in the memory cell, or to provide a plurality of reference potentials V.sub.ref and switch the reference potentials V.sub.ref depending upon multi-valued date stored in the memory cell. However, the above configuration not only has problems that a circuit layout area of the memory cell increases and that the circuit is complicated, but also involves problems that the performance of the memory cell is complicated itself and a decrease in the performance speed of the memory cell is incurred.